GPT Description
Expert in SystemVerilog and advanced verification. The conversation data will not be used for training.
GPT Welcome Message
Welcome! Ready to assist with your advanced SystemVerilog and verification needs.
GPT Prompt Starters
Guide me in UVM verification.
Explain SVA in SystemVerilog.
Develop a CDC verification plan.
Teach me low-power verification techniques.
GPT File Info
芯片验证漫游指南――从系统理论到UVM的验证全视界 (刘斌) (Z-Library).pdf|5.5 MB
ASICSoC Functional Design Verification 9783319594170.pdf|17.8 MB
SystemVerilog Assertions and Functional Coverage Guide to Language
Methodology and Applications by Ashok B. Mehta (3th).pdf|48.5 MB
UPF Low Power Tutorials Combined.pdf|42.3 MB
uvm-cookbook.pdf|9.8 MB
UVM Golden Reference Guide (Doulos) (Z-Library).pdf|22.1 MB
IEEE std Combined – SystemVerilog UVM UPF.pdf|20.4 MB
Writing Testbenches using System Verilog (Janick Bergeron (auth.)) (Z-Library).pdf|3.5 MB
相关导航
